This invention relates generally to optical transmission systems and, more particularly, to error correction schemes for high speed optical transmission systems.
Optical transmission systems that operate at high transmission rates, such as Synchronous Optical Network/Synchronous Digital Hierarchy (SONET/SDH) systems operating at 10 Gb/s, are known to be susceptible to signal-to-noise error impairments as well as impairments associated with optical amplifiers. Among other problems, these impairments can cause unacceptable bit error rates on high speed optical links which carry both voice and data traffic. For example, when multiple fiber optical amplifiers are cascaded in a long haul optical communication system, the resulting noise accumulation from the fiber optical amplifiers imposes a floor on the bit error rate performance of a link (i.e., lowest attainable bit error rate).
Forward error correction (FEC) has been in use for many years to improve channel reliability in communication systems. However, applying forward error correction in SONET/SDH systems presents many challenges. In particular, inserting a forward error correction code into SONET/SDH transmission frames is very difficult given the limited amount of unused overhead. Furthermore, forward error correction schemes require a substantial amount of memory for buffering large amounts of data at the receiver in a SONET/SDH system. Delays associated with processing forward error correction in a SONET/SDH system are also a problem, especially for higher rate systems.
In one proposed scheme described by W. Grover et al. in Design and Characterization of an Error-Correcting Code for the SONET STS-1Tributary, IEEE Transactions on Communications, Vol. 38, No. 4, Apr. 1990, forward error correction is applied on a Synchronous Transport Signal basis whereby an entire STS-1 frame is mapped into a forward error correction block. Because an entire frame must be buffered, the delay is approximately 125 xcexcs or more. This scheme also requires unused overhead bytes in an STS-1 frame for carrying the forward error correction code. As is well known, unused overhead in an STS-1 frame is very limited. Scaling to higher rates using this STS-1 based error correction scheme is problematic due to implementation complexity, buffering requirements, and processing delays. In particular, as the transmission rate increases, the number of required forward error correction blocks increases thus increasing the amount of buffering and associated processing delays. For example, applying this error correction scheme to a STS-192 signal would require 192 blocks (i.e., independent forward error correction algorithms) and 192 logical buffers with a total buffer size approaching one million bits.
In another proposed scheme, a forward error correction code is applied over three rows of a SONET STS-3 signal (e.g., one-third of a frame). Although this approach requires less overhead as compared to the previous approach, this scheme still requires buffering for one-third of a frame with an associated delay of approximately 45 xcexcs. Furthermore, this scheme also requires multiple forward error correcting algorithms for processing the 3-row block. Scaling to higher rates is also problematic for the same reasons previously set forth. For example, applying this error correction scheme to a STS-192 signal would require parallel processing of at least 64 forward error correction algorithms and buffering for approximately 414,720 bits.
U.S. Pat. No. 5,574,717 describes an approach for applying error correction to a Synchronous Digital Hierarchy (SDH) Synchronous Transport Module (STM-1) signaling structure, which is equivalent in rate to a SONET STS-3c signal (e.g., 155 MB/s). Scaling to higher rates such as a STM-64 signal, which is equivalent in rate to a SONET STS-192 signal, is also problematic because of buffering requirements (e.g., an entire frame) and delay (e.g., approximately 125 xcexcs). Moreover, this scheme would require parallel processing of 64 forward error correction algorithms.
Memory requirements and processing delays associated with the application of forward error correction in high speed optical transmissions are substantially reduced according to the principles of the invention by mapping a forward error correction code on a row-by-row basis into unused overhead bytes in a high bit rate signal frame. By applying the forward error correction code to an entire row of the signal frame on a row by row basis, approximately one row needs to be stored at a time thereby reducing the total memory requirements for forward error correction processing. Using SONET as an exemplary application, approximately {fraction (1/9)}th of the entire SONET frame (e.g., one of nine rows) needs to be buffered for forward error correction processing as compared with an entire SONET frame or one-third of a SONET frame as in prior arrangements. Less memory translates to lower cost and less complexity for implementing forward error correction. Furthermore, delay is reduced as a result of the reduced buffering requirements and processing.
In one illustrative embodiment of the invention, four forward error correction (FEC) blocks are provided for each row for a total of 36 FEC blocks for a frame. Each FEC block comprises four bytes of correction bits for a total of 32 correction bits. These 32 correction bits are mapped to unused overhead and are used for correcting errors in one block of one row of a signal frame, wherein one block covers xc2xcth of the row. Other unused overhead bytes in the row may be used to carry error detection codes to facilitate the judicious control of forward error correction. In particular, error detection techniques, such as bit interleaved parity (BIP), cyclic redundancy checks (CRC), and the like, can be used for detecting multiple errors in a row to determine when forward error correction should be disabled. For example, if a single bit error correcting code is employed, then error correction can be disabled to avoid false corrections if more than one error is detected. Other unused overhead bytes may also be used to provide in-band maintenance capabilities, e.g., to carry control bytes for causing error correction to be appropriately enabled or disabled at the receiver.
Using a row-by-row mapping approach yields a significant reduction in delay and reduces the amount of memory needed for error correction processing as compared with the prior arrangements. For example, because only one row needs to be buffered and processed at a time, delay for a 10 Gb/s STS-192 signal can be reduced to approximately 15 xcexcs is or less (approximately {fraction (1/9)}th of a 125 xcexcs frame) and memory can be reduced to approximately 17K bytes, both of which are significant improvements over existing forward error correction schemes contemplated for SONET/SDH systems. Moreover, the mapping scheme according to the principles of the invention uses significantly less overhead and does not require parallel processing of a large number of forward error correction algorithms as in prior arrangements. Advantageously, the mapping scheme maintains the structure of the signal and is suitable for various payload rates, e.g., STS-3/3c, STS-12/12c, STS-48/48c, STS-192/192c, as well as higher rate signals that may be used in future applications.